SPI (Serial Peripheral Interface) - synchronous serial data transfer standard in full-duplex mode, designed to provide a simple and inexpensive pair of microcontrollers and peripherals. SPI is also sometimes called a four interface. 
In contrast to the standard serial port, SPI is a synchronous interface in which every transmission is synchronized with the common clock signal generated by a master device (CPU). Host (slave) Peripherals getting bit sequence synchronizes with the clock signal. By one serial peripheral interface master chip can join several chips. The master selects the slave to transmit a signal activating the "choice of the crystal" on the slave chip. Peripherals are not selected processor does not participate in the transfer on SPI. 
In SPI uses four digital signal: 
• MOSI - Master Out, Slave. Is used to transfer data from the master to the slave. 
• MISO - Master In, Slave Out. Is used to transfer data from the slave master. 
• SCLK - serial clock. Serves to transmit the clock signal for the slaves. 
• CS or SS - chip select, the choice of the slave. 
The transfer is made packages. The packet length is usually 1 byte, wherein a known implementation of a SPI packet length, e.g., 4 bits. The master initiates the communication cycle installing low level at pin slave select (SS) of the device with which you want to connect. At a high level signal SS: 
• slave circuitry is active; 
• MISO pin is put "exit"; 
• SCK clock signal from the master and slave is seen reading on the MOSI input values ​​transmitted from the host bits and the shift register of the slave. 
Data to be transmitted master and slave is placed in the shift registers. Thereafter, the host device begins to generate clock pulses on line SCK, which leads to the interchange of data. Data transfer is made bit by bit from the top floor of the MOSI line and the slave through MISO. Transmission is usually starting with the high-order bits, but some manufacturers allow reordering bit software methods. After each transmission of a data packet, the master device in order to synchronize the slave SS may transfer line to a high state